1. Technical Field
The present invention relates to a test apparatus, a transmission apparatus, a receiving apparatus, a test method, a transmission method, and a receiving method.
2. Related Art
Patent Document 1 discloses a test apparatus that tests a device under test outputting a signal with a clock embedded therein. The test apparatus includes a CDR (Clock Data Recovery) circuit. The CDR circuit contains a PLL circuit that outputs a recovered clock having a frequency that is a prescribed multiple of the frequency of a reference clock supplied thereto and a phase obtained by delaying the phase of the reference clock by a delay amount supplied thereto, and also a phase comparator that detects the phase difference between the recovered clock and the clock embedded in a data signal from the device under test. The CDR circuit controls the delay amount supplied to the PLL circuit according to the phase difference. The test apparatus acquires the output signal according to the recovered clock. For example, see paragraphs 0017, 0023, and 0024 of Patent Document 1.
Patent Document 1: Japanese Patent Application Publication No. 2008-28628
A phase comparator that compares the phase of a recovered clock to the phase of a data signal from a device usually outputs information indicating that the state of the recovered clock is earlier or later than the data signal from the device under test. When the device under test outputs a burst signal that remains unchanged for a long period, such a phase comparator outputs information indicating either the early state or the late state over a long period. In this case, while the device under test is outputting the burst signal, the phase of the recovered clock is delayed or advanced in only one direction, and therefore the recovered clock exits a phase-locked state with respect to the device under test.
In this state, when the device under test again outputs the data signal and testing is resumed, the recovered clock is not locked with respect to the data signal, and therefore the test apparatus cannot correctly acquire the data signal. As a result, the test apparatus must wait until the recovered clock is locked with respect to the data signal, which causes an increase in the overall testing time. This problem occurs when a signal with a clock embedded therein is supplied from the test apparatus to the device under test, and also when a signal with a clock embedded therein is exchanged between two or more apparatuses, which are not limited to test apparatuses.